VHDL ile Clock Domain Crossing Tasarımı

Aşağıda A saat darbesi frekansında mevcut bir sinyalin B saat darbesi frekansında oluşturulmasını sağlayan VHDL kodları aşağıda verilmiştir.

  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3.  
  4.  
  5. entity clk_bridge is
  6. Generic(
  7. CLK_COMPARE : integer range 0 to 1 := 0; --if in_clk_A > in_clk_B; 0 else 1;
  8. DATA_WIDTH : integer := 8
  9.  
  10. );
  11. Port (
  12. in_rst : in std_logic;
  13. in_clk_A : in std_logic;
  14. in_clk_B : in std_logic;
  15. in_data_A_vld : in std_logic;
  16. in_data_A : in std_logic_vector(DATA_WIDTH - 1 downto 0);
  17. out_data_B : out std_logic_vector(DATA_WIDTH - 1 downto 0);
  18. out_data_B_vld : out std_logic
  19.  
  20. );
  21. end clk_bridge;
  22.  
  23. architecture Behavioral of clk_bridge is
  24.  
  25. component cdc_down
  26. generic(
  27. DATA_WIDTH : integer := 8
  28. );
  29. Port (
  30. in_rst : in std_logic;
  31. in_clk_A : in std_logic;
  32. in_clk_B : in std_logic;
  33. in_data_A_vld : in std_logic;
  34. in_data_A : in std_logic_vector(DATA_WIDTH - 1 downto 0);
  35. out_data_B : out std_logic_vector(DATA_WIDTH - 1 downto 0);
  36. out_data_B_vld : out std_logic
  37.  
  38. );
  39. end component;
  40.  
  41. component cdc_up
  42. generic(
  43. DATA_WIDTH : integer := 8
  44. );
  45. Port (
  46. in_rst : in std_logic;
  47. in_clk_A : in std_logic;
  48. in_clk_B : in std_logic;
  49. in_data_A_vld : in std_logic;
  50. in_data_A : in std_logic_vector(DATA_WIDTH - 1 downto 0);
  51. out_data_B : out std_logic_vector(DATA_WIDTH - 1 downto 0);
  52. out_data_B_vld : out std_logic
  53. );
  54. end component;
  55. begin
  56.  
  57. cdc_down_if : if CLK_COMPARE = 0 generate
  58. cdc_down_map : cdc_down
  59. generic map(
  60. DATA_WIDTH => DATA_WIDTH
  61. )
  62. Port map(
  63. in_rst => in_rst,
  64. in_clk_A => in_clk_A,
  65. in_clk_B => in_clk_B,
  66. in_data_A_vld => in_data_A_vld,
  67. in_data_A => in_data_A,
  68. out_data_B => out_data_B,
  69. out_data_B_vld => out_data_B_vld
  70. );
  71. end generate cdc_down_if;
  72. cdc_up_if : if CLK_COMPARE = 1 generate
  73. cdc_up_map : cdc_up
  74. generic map(
  75. DATA_WIDTH => DATA_WIDTH
  76. )
  77. Port map(
  78. in_rst => in_rst,
  79. in_clk_A => in_clk_A,
  80. in_clk_B => in_clk_B,
  81. in_data_A_vld => in_data_A_vld,
  82. in_data_A => in_data_A,
  83. out_data_B => out_data_B,
  84. out_data_B_vld => out_data_B_vld
  85. );
  86. end generate cdc_up_if;
  87.  
  88. end Behavioral;
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3.  
  4. entity cdc_down is
  5. generic(
  6. DATA_WIDTH : integer := 8
  7. );
  8. Port (
  9. in_rst : in std_logic;
  10. in_clk_A : in std_logic;
  11. in_clk_B : in std_logic;
  12. in_data_A_vld : in std_logic;
  13. in_data_A : in std_logic_vector(DATA_WIDTH - 1 downto 0);
  14. out_data_B : out std_logic_vector(DATA_WIDTH - 1 downto 0);
  15. out_data_B_vld : out std_logic
  16.  
  17. );
  18. end cdc_down;
  19.  
  20. architecture Behavioral of cdc_down is
  21.  
  22. signal r_data_A : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
  23. signal r_data_B : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
  24. signal r_handshake_A : std_logic := '0';
  25. signal r_handshake_B : std_logic := '0';
  26.  
  27. begin
  28.  
  29. out_data_B <= r_data_B;
  30. out_data_B_vld <= r_handshake_B;
  31.  
  32. process(in_clk_A, in_rst)
  33. begin
  34. if in_rst = '1' then
  35. r_handshake_A <= '0';
  36. r_data_A <= (others => '0');
  37.  
  38. elsif rising_edge(in_clk_A) then
  39. if in_data_A_vld = '1' and r_handshake_A = '0' then
  40. r_data_A <= in_data_A;
  41. r_handshake_A <= '1';
  42. else
  43. if r_handshake_B = '1' then
  44. r_handshake_A <= '0';
  45. end if;
  46. end if;
  47. end if;
  48. end process;
  49.  
  50. process(in_clk_B, in_rst)
  51. begin
  52. if in_rst = '1' then
  53. r_handshake_B <= '0';
  54. r_data_B <= (others => '0');
  55. elsif rising_edge(in_clk_B) then
  56. if r_handshake_B = '0' and r_handshake_A = '1' then
  57. r_handshake_B <= '1';
  58. r_data_B <= r_data_A;
  59. elsif r_handshake_A = '0' then
  60. r_handshake_B <= '0';
  61. end if;
  62. end if;
  63. end process;
  64.  
  65. end Behavioral;
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  15. /* phone */
  16. document.write('');
  17. (adsbygoogle = window.adsbygoogle || []).push({});
  18. }
  19.  
  20.  
  21.  
  22.  
  23.  
  24.  
  25. library IEEE;
  26. use IEEE.STD_LOGIC_1164.ALL;
  27.  
  28. entity cdc_up is
  29. generic(
  30. DATA_WIDTH : integer := 8
  31. );
  32. Port (
  33. in_rst : in std_logic;
  34. in_clk_A : in std_logic;
  35. in_clk_B : in std_logic;
  36. in_data_A_vld : in std_logic;
  37. in_data_A : in std_logic_vector(DATA_WIDTH - 1 downto 0);
  38. out_data_B : out std_logic_vector(DATA_WIDTH - 1 downto 0);
  39. out_data_B_vld : out std_logic
  40. );
  41. end cdc_up;
  42.  
  43. architecture Behavioral of cdc_up is
  44. signal r_data_cnt : std_logic_vector(3 downto 0) := (others => '0');
  45. begin
  46.  
  47. out_data_B <= in_data_A when r_data_cnt(3 downto 2) = "01" else (others => '0');
  48. out_data_B_vld <= '1' when r_data_cnt(3 downto 2) = "01" else '0';
  49.  
  50. process(in_clk_B, in_rst)
  51. begin
  52. if in_rst = '1' then
  53. r_data_cnt <= (others => '0');
  54. elsif rising_edge(in_clk_B) then
  55. r_data_cnt <= r_data_cnt(2 downto 0) & in_data_A_vld;
  56. end if;
  57. end process;
  58. end Behavioral;

 

  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  4.  
  5. entity tb_clk_bridge is
  6. end tb_clk_bridge;
  7.  
  8. architecture Behavioral of tb_clk_bridge is
  9.  
  10. component clk_bridge
  11. Generic(
  12. CLK_COMPARE : integer range 0 to 1 := 0; --if in_clk_1 > in_clk_2; 0 else 1;
  13. DATA_WIDTH : integer := 8
  14.  
  15. );
  16. Port (
  17. in_rst : in std_logic;
  18. in_clk_A : in std_logic;
  19. in_clk_B : in std_logic;
  20. in_data_A_vld : in std_logic;
  21. in_data_A : in std_logic_vector(DATA_WIDTH - 1 downto 0);
  22. out_data_B : out std_logic_vector(DATA_WIDTH - 1 downto 0);
  23. out_data_B_vld : out std_logic
  24. );
  25. end component;
  26.  
  27. constant DATA_WIDTH : integer := 8;
  28. constant PERIOD_CLK_A :time := 10 us;
  29. constant PERIOD_CLK_B :time := 1 us;
  30. signal in_clk_A : std_logic := '0';
  31. signal in_clk_B : std_logic := '0';
  32. signal in_data_A_vld : std_logic := '0';
  33. signal in_data_A : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
  34. signal out_data_B : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
  35. signal out_data_B_vld : std_logic := '0';
  36.  
  37. begin
  38. process
  39. begin
  40. in_clk_A <= '1';
  41. wait for PERIOD_CLK_A / 2;
  42. in_clk_A <= '0';
  43. wait for PERIOD_CLK_A / 2;
  44. end process;
  45.  
  46. process
  47. begin
  48. in_clk_B <= '1';
  49. wait for PERIOD_CLK_B / 2;
  50. in_clk_B <= '0';
  51. wait for PERIOD_CLK_B / 2;
  52. end process;
  53.  
  54. process
  55. begin
  56. in_data_A_vld <= '0';
  57. wait for PERIOD_CLK_A * 19;
  58. in_data_A_vld <= '1';
  59. wait for PERIOD_CLK_A;
  60. end process;
  61.  
  62. process(in_data_A_vld)
  63. begin
  64. if in_data_A_vld = '1' then
  65. in_data_A <= in_data_A + 1;
  66. end if;
  67. end process;
  68.  
  69.  
  70. clk_bridge_map : clk_bridge
  71. Generic map(
  72. CLK_COMPARE => 1, --f_clk_a <= f_clk_b
  73. DATA_WIDTH => DATA_WIDTH
  74. )
  75. Port map(
  76. in_rst => '0',
  77. in_clk_A => in_clk_A,
  78. in_clk_B => in_clk_B,
  79. in_data_A_vld => in_data_A_vld,
  80. in_data_A => in_data_A,
  81. out_data_B => out_data_B,
  82. out_data_B_vld => out_data_B_vld
  83. );
  84.  
  85. end Behavioral;

 

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