Dijital Kronometre Uygulamasının Nexys 4 Kartı Üzerinde Gerçeklenmesi

Aşağıda ayarlanabilir dijital koronometre uygulamasının Nexys 4 kartı üzerinde gerçeklenmesine ait kodlar ve videolar gösterilmiştir. kronometre.vhd dosyası saat kontrol işlemlerinin yapıldığı ana modüldür. Saniye ve dakika ayarları için min_sec_digit_cntrl.vhd  modülü tasarlanmıştır. Saat ayarları için ise hour_digit_cntrl.vhd modülü tasarlanmıştır.

Digital Kronometre tasarımında durdurma ve resetleme özelliği sağlanmıştır. Kronometrenin çalışmasına ilişkin video aşağıdadır.

  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  4. use IEEE.STD_LOGIC_ARITH.ALL;
  5.  
  6. entity kronometre is
  7. generic(
  8. SYS_FREQ : integer := 100_000_000
  9. );
  10. Port(
  11. in_clk : in std_logic;
  12. in_rst : in std_logic;
  13. in_strt_stp : in std_logic;
  14. out_seg : out std_logic_vector(7 downto 0);
  15. out_seg_leds : out std_logic_vector(7 downto 0)
  16. );
  17. end kronometre;
  18.  
  19. architecture Behavioral of kronometre is
  20.  
  21. component hour_digit_cntrl
  22. Port (
  23. in_clk : in std_logic;
  24. in_rst : in std_logic;
  25. in_pulse : in std_logic;
  26. in_inc_right : in std_logic;
  27. in_inc_left : in std_logic;
  28. out_right_digit : out std_logic_vector(3 downto 0);
  29. out_left_digit : out std_logic_vector(3 downto 0)
  30. );
  31. end component;
  32.  
  33. component min_sec_digit_cntrl
  34. Generic(
  35. DIGIT_SIZE : integer := 10
  36. );
  37. Port (
  38. in_clk : in std_logic;
  39. in_rst : in std_logic;
  40. in_pulse : in std_logic;
  41. in_inc : in std_logic;
  42. out_digit : out std_logic_vector(3 downto 0);
  43. out_pulse : out std_logic
  44. );
  45. end component;
  46.  
  47. component bcd2seven_segment
  48. Port (
  49. in_bcd : in std_logic_vector(3 downto 0);
  50. out_seven_segment : out std_logic_vector(7 downto 0)
  51. );
  52. end component;
  53.  
  54.  
  55. component pulse_generator
  56. generic(
  57. FREQ : integer := 100_000_000
  58. );
  59. Port (
  60. in_clk : in std_logic;
  61. in_rst : in std_logic;
  62. in_en : in std_logic;
  63. out_pulse : out std_logic
  64. );
  65. end component;
  66.  
  67. component buton_push
  68. Port (
  69. in_clk : in std_logic;
  70. in_rst : in std_logic;
  71. in_buton : in std_logic;
  72. out_btn_pulse : out std_logic
  73. );
  74. end component;
  75.  
  76.  
  77. type t_Time_Digits is array (0 to 7) of std_logic_vector(3 downto 0);
  78. signal r_Time_Digits : t_Time_Digits := (others=>(others => '0'));
  79.  
  80. signal r_bcd : std_logic_vector(3 downto 0) := (others => '0');
  81. signal r_seg_leds : std_logic_vector(7 downto 0) := (others => '0');
  82. signal r_seg : std_logic_vector(7 downto 0) := "01111111";
  83. signal r_seg_cnt : std_logic_vector(2 downto 0) := (others => '0');
  84. signal r_seg_pulse : std_logic := '0';
  85.  
  86.  
  87. signal r_sec_pulse : std_logic := '0';
  88. signal r_sec_10_pulse : std_logic := '0';
  89. signal r_sec_100_pulse : std_logic := '0';
  90. signal r_sec_right_pulse : std_logic := '0';
  91. signal r_sec_left_pulse : std_logic := '0';
  92. signal r_min_right_pulse : std_logic := '0';
  93. signal r_min_left_pulse : std_logic := '0';
  94.  
  95. signal r_strt_cntrl : std_logic_vector(2 downto 0) := (others=> '0');
  96. signal r_en : std_logic := '0';
  97. signal r_strt_stp_puls : std_logic := '0';
  98. signal r_rst_puls : std_logic := '0';
  99.  
  100.  
  101. begin
  102.  
  103. out_seg_leds <= r_seg_leds;
  104. out_seg <= r_seg;-- f_set_shift(r_seg, r_set_stts, r_set_seg);
  105.  
  106.  
  107. -- hour_digit_cntrl_map : hour_digit_cntrl
  108. -- Port map (
  109. -- in_clk => in_clk,
  110. -- in_rst => r_rst_puls,
  111. -- in_pulse => r_min_left_pulse,
  112. -- in_inc_right => '0',
  113. -- in_inc_left => '0',
  114. -- out_right_digit => r_Time_Digits(1),
  115. -- out_left_digit => r_Time_Digits(0)
  116. -- );
  117.  
  118.  
  119. min_left_digit : min_sec_digit_cntrl
  120. Generic map(
  121. DIGIT_SIZE => 6
  122. )
  123. Port map(
  124. in_clk => in_clk,
  125. in_rst => r_rst_puls,
  126. in_pulse => r_min_right_pulse,
  127. in_inc => '0',
  128. out_digit => r_Time_Digits(2),
  129. out_pulse => r_min_left_pulse
  130. );
  131.  
  132. min_right_digit : min_sec_digit_cntrl
  133. Generic map(
  134. DIGIT_SIZE => 10
  135. )
  136. Port map(
  137. in_clk => in_clk,
  138. in_rst => r_rst_puls,
  139. in_pulse => r_sec_left_pulse,
  140. in_inc => '0',
  141. out_digit => r_Time_Digits(3),
  142. out_pulse => r_min_right_pulse
  143. );
  144.  
  145.  
  146. sec_left_digit : min_sec_digit_cntrl
  147. Generic map(
  148. DIGIT_SIZE => 6
  149. )
  150. Port map(
  151. in_clk => in_clk,
  152. in_rst => r_rst_puls,
  153. in_pulse => r_sec_right_pulse,
  154. in_inc => '0',
  155. out_digit => r_Time_Digits(4),
  156. out_pulse => r_sec_left_pulse
  157. );
  158.  
  159. sec_right_digit : min_sec_digit_cntrl
  160. Generic map(
  161. DIGIT_SIZE => 10
  162. )
  163. Port map(
  164. in_clk => in_clk,
  165. in_rst => r_rst_puls,
  166. in_pulse => r_sec_pulse,
  167. in_inc => '0',
  168. out_digit => r_Time_Digits(5),
  169. out_pulse => r_sec_right_pulse
  170. );
  171.  
  172.  
  173. sec_digit_10 : min_sec_digit_cntrl
  174. Generic map(
  175. DIGIT_SIZE => 10
  176. )
  177. Port map(
  178. in_clk => in_clk,
  179. in_rst => r_rst_puls,
  180. in_pulse => r_sec_10_pulse,
  181. in_inc => '0',
  182. out_digit => r_Time_Digits(6),
  183. out_pulse => r_sec_pulse
  184. );
  185.  
  186. sec_digit_100 : min_sec_digit_cntrl
  187. Generic map(
  188. DIGIT_SIZE => 10
  189. )
  190. Port map(
  191. in_clk => in_clk,
  192. in_rst => r_rst_puls,
  193. in_pulse => r_sec_100_pulse,
  194. in_inc => '0',
  195. out_digit => r_Time_Digits(7),
  196. out_pulse => r_sec_10_pulse
  197. );
  198.  
  199.  
  200. second_100_pulse_map : pulse_generator
  201. generic map(
  202. FREQ => SYS_FREQ / 100
  203. )
  204. Port map (
  205. in_clk => in_clk,
  206. in_rst => r_rst_puls,
  207. in_en => r_en,
  208. out_pulse => r_sec_100_pulse
  209. );
  210.  
  211. -- Enable disable control
  212.  
  213. process(in_clk, r_rst_puls)
  214. begin
  215. if r_rst_puls = '1' then
  216. r_en <= '0';
  217. elsif rising_edge(in_clk) then
  218. if r_strt_stp_puls = '1' then
  219. r_en <= not r_en;
  220. end if;
  221. end if;
  222. end process;
  223.  
  224.  
  225. strt_stop_map : buton_push
  226. port map(
  227. in_clk => in_clk,
  228. in_rst => r_rst_puls,
  229. in_buton => in_strt_stp,
  230. out_btn_pulse => r_strt_stp_puls
  231. );
  232.  
  233.  
  234. -- display control
  235.  
  236. process(in_clk, r_rst_puls)
  237. begin
  238. if r_rst_puls = '1' then
  239. r_seg_cnt <= (others => '0');
  240. r_bcd <= (others => '0');
  241.  
  242. elsif rising_edge(in_clk) then
  243. if r_seg_pulse = '1' then
  244. r_bcd <= r_Time_Digits(7 - conv_integer(r_seg_cnt));
  245. if r_seg_cnt = 7 then
  246. r_seg_cnt <= (others => '0');
  247. else
  248. r_seg_cnt <= r_seg_cnt + 1;
  249. end if;
  250. end if;
  251. end if;
  252. end process;
  253.  
  254. bcd2seven_segment_map : bcd2seven_segment
  255. Port map(
  256. in_bcd => r_bcd,
  257. out_seven_segment => r_seg_leds
  258. );
  259.  
  260. process(in_clk, r_rst_puls)
  261. begin
  262. if r_rst_puls = '1' then
  263. r_seg <= "01111111";
  264.  
  265. elsif rising_edge(in_clk) then
  266. if r_seg_pulse = '1' then
  267. r_seg <= r_seg(6 downto 0) & r_seg(7);
  268.  
  269. end if;
  270. end if;
  271. end process;
  272.  
  273. seg_pulse_map : pulse_generator
  274. generic map(
  275. FREQ => 10_000
  276. )
  277. Port map (
  278. in_clk => in_clk,
  279. in_rst => r_rst_puls,
  280. in_en => '1',
  281. out_pulse => r_seg_pulse
  282. );
  283.  
  284.  
  285. rst_contrl_map : buton_push
  286. port map(
  287. in_clk => in_clk,
  288. in_rst => '0',
  289. in_buton => in_rst,
  290. out_btn_pulse => r_rst_puls
  291. );
  292.  
  293. end Behavioral;

 

  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  4. use IEEE.STD_LOGIC_ARITH.ALL;
  5.  
  6. entity hour_digit_cntrl is
  7. Port (
  8. in_clk : in std_logic;
  9. in_rst : in std_logic;
  10. in_pulse : in std_logic;
  11. in_inc_right : in std_logic;
  12. in_inc_left : in std_logic;
  13. out_right_digit : out std_logic_vector(3 downto 0);
  14. out_left_digit : out std_logic_vector(3 downto 0)
  15. );
  16. end hour_digit_cntrl;
  17.  
  18. architecture Behavioral of hour_digit_cntrl is
  19.  
  20. signal r_right_digit : std_logic_vector(3 downto 0);
  21. signal r_left_digit : std_logic_vector(3 downto 0);
  22.  
  23. begin
  24.  
  25. out_right_digit <= r_right_digit;
  26. out_left_digit <= r_left_digit;
  27.  
  28. process(in_clk, in_rst)
  29. begin
  30. if in_rst = '1' then
  31. r_right_digit <= (others => '0');
  32. r_left_digit <= (others => '0');
  33. elsif rising_edge(in_clk) then
  34. if in_pulse = '1' then
  35. if (r_left_digit /= 2 and r_right_digit = 9) or
  36. (r_left_digit = 2 and r_right_digit = 3) then
  37. r_right_digit <= (others => '0');
  38. if r_left_digit = 2 then
  39. r_left_digit <= (others => '0');
  40. else
  41. r_left_digit <= r_left_digit + 1;
  42. end if;
  43. else
  44. r_right_digit <= r_right_digit + 1;
  45. end if;
  46. end if;
  47.  
  48. if in_inc_right = '1' then
  49. if (r_left_digit /= 2 and r_right_digit = 9) or
  50. (r_left_digit = 2 and r_right_digit = 3) then
  51. r_right_digit <= (others => '0');
  52. else
  53. r_right_digit <= r_right_digit + 1;
  54. end if;
  55. end if;
  56.  
  57. if in_inc_left = '1' then
  58. if r_left_digit = 2 then
  59. r_left_digit <= (others => '0');
  60. else
  61. r_left_digit <= r_left_digit + 1;
  62. end if;
  63. end if;
  64. end if;
  65. end process;
  66.  
  67.  
  68. end Behavioral;

 

  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  4. use IEEE.STD_LOGIC_ARITH.ALL;
  5.  
  6. entity min_sec_digit_cntrl is
  7. Generic(
  8. DIGIT_SIZE : integer := 10
  9. );
  10. Port (
  11. in_clk : in std_logic;
  12. in_rst : in std_logic;
  13. in_pulse : in std_logic;
  14. in_inc : in std_logic;
  15. out_digit : out std_logic_vector(3 downto 0);
  16. out_pulse : out std_logic
  17. );
  18. end min_sec_digit_cntrl;
  19.  
  20. architecture Behavioral of min_sec_digit_cntrl is
  21.  
  22. signal r_digit : std_logic_vector(3 downto 0) := (others => '0');
  23. signal r_pulse : std_logic := '0';
  24.  
  25. begin
  26.  
  27. out_digit <= r_digit;
  28. out_pulse <= r_pulse;
  29.  
  30. process(in_clk, in_rst)
  31. begin
  32. if in_rst = '1' then
  33. r_digit <= (others => '0');
  34. r_pulse <= '0';
  35. elsif rising_edge(in_clk) then
  36. r_pulse <= '0';
  37. if in_pulse = '1' then
  38. if r_digit = DIGIT_SIZE - 1 then
  39. r_pulse <= '1';
  40. r_digit <= (others => '0');
  41. else
  42. r_digit <= r_digit + 1;
  43. end if;
  44. end if;
  45.  
  46. if in_inc = '1' then
  47. if r_digit = DIGIT_SIZE - 1 then
  48. r_digit <= (others => '0');
  49. else
  50. r_digit <= r_digit + 1;
  51. end if;
  52. end if;
  53. end if;
  54. end process;
  55.  
  56. end Behavioral;

 

  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3.  
  4. entity bcd2seven_segment is
  5. Port (
  6. in_bcd : in std_logic_vector(3 downto 0);
  7. out_seven_segment : out std_logic_vector(7 downto 0)
  8. );
  9. end bcd2seven_segment;
  10.  
  11. architecture Behavioral of bcd2seven_segment is
  12.  
  13. signal r_seven_segment : std_logic_vector(7 downto 0) := (others => '0');
  14.  
  15. begin
  16.  
  17. out_seven_segment <= r_seven_segment;
  18.  
  19. process(in_bcd)
  20. begin
  21. case in_bcd is
  22. when "0000" =>
  23. r_seven_segment <= "10000001";
  24. when "0001" =>
  25. r_seven_segment <= "11001111";
  26. when "0010" =>
  27. r_seven_segment <= "10010010";
  28. when "0011" =>
  29. r_seven_segment <= "10000110";
  30. when "0100" =>
  31. r_seven_segment <= "11001100";
  32. when "0101" =>
  33. r_seven_segment <= "10100100";
  34. when "0110" =>
  35. r_seven_segment <= "10100000";
  36. when "0111" =>
  37. r_seven_segment <= "10001111";
  38. when "1000" =>
  39. r_seven_segment <= "10000000";
  40. when "1001" =>
  41. r_seven_segment <= "10000100";
  42. when others =>
  43. r_seven_segment <= "00000000";
  44. end case;
  45. end process;
  46.  
  47.  
  48. end Behavioral;

 

  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3.  
  4. entity buton_push is
  5. Port (
  6. in_clk : in std_logic;
  7. in_rst : in std_logic;
  8. in_buton : in std_logic;
  9. out_btn_pulse : out std_logic
  10. );
  11. end buton_push;
  12.  
  13. architecture Behavioral of buton_push is
  14.  
  15. signal r_btn_cntrl : std_logic_vector(2 downto 0) := (others=> '0');
  16. signal r_btn_pulse : std_logic := '0';
  17.  
  18. begin
  19.  
  20. out_btn_pulse <= r_btn_pulse;
  21.  
  22. process(in_clk, in_rst)
  23. begin
  24. if in_rst = '1' then
  25. r_btn_pulse <= '0';
  26. elsif rising_edge(in_clk) then
  27. r_btn_pulse <= '0';
  28. if r_btn_cntrl(2 downto 1) = "01" then
  29. r_btn_pulse <= '1';
  30. end if;
  31. end if;
  32. end process;
  33.  
  34.  
  35. process(in_clk, in_rst)
  36. begin
  37. if in_rst = '1' then
  38. r_btn_cntrl <= (others=> '0');
  39. elsif rising_edge(in_clk) then
  40. r_btn_cntrl <= r_btn_cntrl(1 downto 0) & in_buton;
  41. end if;
  42. end process;
  43.  
  44. end Behavioral;

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity pulse_generator is
	generic(
		FREQ : integer := 100_000_000
	);
	Port ( 
		in_clk : in std_logic;
		in_rst : in std_logic;
		in_en : in std_logic;
		out_pulse : out std_logic
	);
end pulse_generator;
 
architecture Behavioral of pulse_generator is
 
	signal r_pulse : std_logic := '0';
	signal r_cnt : integer := 0;
 
begin
 
	out_pulse <= r_pulse;
 
	process(in_clk, in_rst)
	begin
		if in_rst = '1' then
			r_cnt<= 0;
			r_pulse <= '0';
 
		elsif rising_edge(in_clk) then
		  if in_en = '1' then
			if r_cnt = FREQ - 1 then
				r_pulse <= '1';
				r_cnt<= 0;
			else
				r_pulse <= '0';
				r_cnt <= r_cnt + 1;			
			end if;
		  end if;	
		end if;
	end process;
 
end Behavioral;

 

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