Rastgele Sayı Üreteci Modülünün VHDL ile Gerçeklenmesi

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.lfsr_packet.all;
 
entity lfsr is
	Generic(
		INIT_VALUE : std_logic_vector(DATA_WIDTH - 1 downto 0) := X"A47C"
	);
	Port ( 
		in_clk : in std_logic;
		in_rst : in std_logic;
		out_rnd_data : out std_logic_vector(DATA_WIDTH - 1 downto 0)	
	);
end lfsr;
 
architecture Behavioral of lfsr is
 
	signal r_rnd_data : std_logic_vector(DATA_WIDTH - 1 downto 0) := INIT_VALUE;
 
begin
 
	out_rnd_data <= r_rnd_data;
 
	process(in_clk, in_rst)
	begin
		if in_rst = '1' then
			r_rnd_data <= INIT_VALUE;
		elsif rising_edge(in_clk) then
			r_rnd_data <= f_lfsr(r_rnd_data, c_POLYNOM);
		end if;
	end process;
 
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
package lfsr_packet is
 
	constant	DATA_WIDTH : integer := 16;
	constant	PLOY_LENGTH : integer := 3;
 
	type t_POLYNOM is array (0 to PLOY_LENGTH - 1) of integer range 0 to DATA_WIDTH - 1; 
	constant c_POLYNOM : t_POLYNOM := (13, 12, 10);
 
    function f_lfsr(data : std_logic_vector(DATA_WIDTH - 1 downto 0); POLYNOM : t_POLYNOM ) return std_logic_vector;
 
end lfsr_packet;
 
package body lfsr_packet is
 
	function f_lfsr(data : std_logic_vector(DATA_WIDTH - 1 downto 0); POLYNOM : t_POLYNOM ) return std_logic_vector is
		variable v_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
		variable v_zero : std_logic;
	begin
		v_data := data;
		v_zero := v_data(0);
		v_data(DATA_WIDTH - 2 downto 0) := v_data(DATA_WIDTH - 1 downto 1);
		v_data(DATA_WIDTH - 1) := v_zero;
    	for n_j in 0 to PLOY_LENGTH - 1 loop
			v_data(POLYNOM(n_j)) := v_data(POLYNOM(n_j)) xor v_zero;            
		end loop;	
		return v_data;
	end f_lfsr;	
 
end package body;