NEXYS4 DDR 7 Segment Display 0-F Counter

Bu uygulamada kart üzerindeki 7 segment display belirlediğimiz süre kadar bekleyerek(1sn) 0 dan F e kadar saydırıldı.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
 
entity counter is
  Port ( 
    in_clk : in std_logic;
    in_rst : in std_logic;
    in_giris : in std_logic_vector(3 downto 0);
    out_disp_sec : out std_logic_vector(7 downto 0);
    out_cikis : out std_logic_vector(7 downto 0)
  );
end counter;
 
architecture Behavioral of counter is
 
    type t_display_ekran is array (0 to 15) of std_logic_vector(7 downto 0);
    constant DISP_EKRAN : t_display_ekran := ("10000001", "11001111", "10010010",
    "10000110", "11001100", "10100100", "10100000", "10001111", "10000000", 
    "10000100", "10001000", "11100000", "10110001", "11000010", "10110000", 
    "10111000");
 
    signal r_giris : std_logic_vector(3 downto 0) := (others => '0');
    signal r_cikis : std_logic_vector(7 downto 0) := (others => '0');
    signal clk_1hz : std_logic ;
    signal sayac : integer range 0 to 100000000 ;  -- 100mhz sayac oluşturuldu 
    signal i: integer range 0 to 15;
 
begin
 
    out_disp_sec <= "00000000";
    out_cikis <= r_cikis;
 
 
    clk_1hz_process : process( in_clk,in_rst )
        begin                 
          if(rising_edge(in_clk)) then 
              if (sayac < 100000000) then 
                  sayac <= sayac + 1 ;
                  clk_1hz <= '0';
              else
                  sayac <= 0;
                  clk_1hz <= '1';
              end if;
          end if;
    end process clk_1hz_process;    
 
 
    process (clk_1hz)
        begin
            if (rising_edge(clk_1hz)) then
               i <= 0;
               r_cikis <= DISP_EKRAN(conv_integer(i));
               i <= i +1;     
            end if;
        end process;
end Behavioral;
## Clock signal
#Bank = 35, Pin name = IO_L12P_T1_MRCC_35,                                      Sch name = CLK100MHZ
set_property PACKAGE_PIN E3 [get_ports in_clk]                                                  
        set_property IOSTANDARD LVCMOS33 [get_ports in_clk]
        create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports in_clk]
 
## Switches
set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { in_giris[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { in_giris[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { in_giris[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { in_giris[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
 
##7 segment display
#Bank = 34, Pin name = IO_L2N_T0_34,                                            Sch name = CA
set_property PACKAGE_PIN T10 [get_ports {out_cikis[6]}]                                 
        set_property IOSTANDARD LVCMOS33 [get_ports {out_cikis[6]}]
#Bank = 34, Pin name = IO_L3N_T0_DQS_34,                                        Sch name = CB
set_property PACKAGE_PIN R10 [get_ports {out_cikis[5]}]                                 
        set_property IOSTANDARD LVCMOS33 [get_ports {out_cikis[5]}]
#Bank = 34, Pin name = IO_L6N_T0_VREF_34,                                       Sch name = CC
set_property PACKAGE_PIN K16 [get_ports {out_cikis[4]}]                                 
        set_property IOSTANDARD LVCMOS33 [get_ports {out_cikis[4]}]
#Bank = 34, Pin name = IO_L5N_T0_34,                                            Sch name = CD
set_property PACKAGE_PIN K13 [get_ports {out_cikis[3]}]                                 
        set_property IOSTANDARD LVCMOS33 [get_ports {out_cikis[3]}]
#Bank = 34, Pin name = IO_L2P_T0_34,                                            Sch name = CE
set_property PACKAGE_PIN P15 [get_ports {out_cikis[2]}]                                 
        set_property IOSTANDARD LVCMOS33 [get_ports {out_cikis[2]}]
#Bank = 34, Pin name = IO_L4N_T0_34,                                            Sch name = CF
set_property PACKAGE_PIN T11 [get_ports {out_cikis[1]}]                                 
        set_property IOSTANDARD LVCMOS33 [get_ports {out_cikis[1]}]
#Bank = 34, Pin name = IO_L6P_T0_34,                                            Sch name = CG
set_property PACKAGE_PIN L18 [get_ports {out_cikis[0]}]                                 
        set_property IOSTANDARD LVCMOS33 [get_ports {out_cikis[0]}]
 
#Bank = 34, Pin name = IO_L16P_T2_34,                                           Sch name = DP
set_property PACKAGE_PIN H15 [get_ports {out_cikis[7]}]                                                 
        set_property IOSTANDARD LVCMOS33 [get_ports {out_cikis[7]}]
 
#Bank = 34, Pin name = IO_L18N_T2_34,                                           Sch name = AN0
set_property PACKAGE_PIN J17 [get_ports {out_disp_sec[0]}]                                      
        set_property IOSTANDARD LVCMOS33 [get_ports {out_disp_sec[0]}]
#Bank = 34, Pin name = IO_L18P_T2_34,                                           Sch name = AN1
set_property PACKAGE_PIN J18 [get_ports {out_disp_sec[1]}]                                      
        set_property IOSTANDARD LVCMOS33 [get_ports {out_disp_sec[1]}]
#Bank = 34, Pin name = IO_L4P_T0_34,                                            Sch name = AN2
set_property PACKAGE_PIN T9 [get_ports {out_disp_sec[2]}]                                       
        set_property IOSTANDARD LVCMOS33 [get_ports {out_disp_sec[2]}]
#Bank = 34, Pin name = IO_L13_T2_MRCC_34,                                       Sch name = AN3
set_property PACKAGE_PIN J14 [get_ports {out_disp_sec[3]}]                                      
        set_property IOSTANDARD LVCMOS33 [get_ports {out_disp_sec[3]}]
#Bank = 34, Pin name = IO_L3P_T0_DQS_34,                                        Sch name = AN4
set_property PACKAGE_PIN P14 [get_ports {out_disp_sec[4]}]                                      
        set_property IOSTANDARD LVCMOS33 [get_ports {out_disp_sec[4]}]
#Bank = 34, Pin name = IO_L16N_T2_34,                                           Sch name = AN5
set_property PACKAGE_PIN T14 [get_ports {out_disp_sec[5]}]                                      
        set_property IOSTANDARD LVCMOS33 [get_ports {out_disp_sec[5]}]
#Bank = 34, Pin name = IO_L1P_T0_34,                                            Sch name = AN6
set_property PACKAGE_PIN K2 [get_ports {out_disp_sec[6]}]                                       
        set_property IOSTANDARD LVCMOS33 [get_ports {out_disp_sec[6]}]
#Bank = 34, Pin name = IO_L1N_T034,                                                     Sch name = AN7
set_property PACKAGE_PIN U13 [get_ports {out_disp_sec[7]}]                                      
        set_property IOSTANDARD LVCMOS33 [get_ports {out_disp_sec[7]}]
 
##Bank = 14, Pin name = IO_L21P_T3_DQS_14,                                      Sch name = BTND
set_property PACKAGE_PIN P18 [get_ports in_rst]                                         
        set_property IOSTANDARD LVCMOS33 [get_ports in_rst]

 

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